Integrated circuits are subject to damage from electrostatic discharge (ESD) events. A person can cause such an event by touching an input lead to a device or a conductor connected to that lead. Such discharges are characterized by voltages in the kilovolt range and instantaneous currents in the ampere range. As circuit geometries are reduced to provide faster and more complex integrated circuits, the vulnerability of the integrated circuits to such events increases.
To protect such circuits, a protection circuit is often attached to the input pads on the chip. The circuit shorts the pad to the substrate on the chip if the voltage on the pad exceeds a predetermined value. Numerous protection circuits for use in CMOS circuitry are known to the art. The simplest form of ESD protection circuit consists of one or more diodes connected in series to form a chain that is connected between the pad and the substrate. As long as the voltage on the pad is less than the diode threshold, little current flows from the pad to ground through the diode chain. If the voltage is greater than the diode threshold of the chain, the circuit will conduct charge from the pad to ground, and hence, prevent the voltage on the pad from increasing much beyond the diode threshold. The voltage at which the chain conducts is determined by the number of diodes in the chain.
Unfortunately, these circuits cannot be used in charge-coupled devices (CCDs). Imaging chips that are utilized in a wide range of camera devices are based on CCD arrays. The CCD structure can be viewed as a number of columns that are divided into pixels whose boundaries can be moved to read out the charge by shifting the charge down the columns. The boundaries of the pixels and the charge shifting mechanism are implemented with a plurality of gates that overlie the portion of the substrate in which the columns are located. Each pixel on the chip has a plurality of gates. The gates are separated from the substrate by a thin oxide layer. If the potential difference between the gates and the substrate is sufficiently high, the oxide layer can be damaged. For example, a short can be formed from the gate to the substrate. As will be discussed in more detail below, each gate belongs to a specific class, and all of the gates in a class are connected together. Hence, such a short effectively shorts all of the gates in that class and renders the chip, or a large portion thereof, inoperative. Even if the resultant oxide damage does not short the gate to the substrate, the oxide damage can result in long-term reliability problems that lead to premature device failure. Unlike CMOS circuitry, CCD designs do not lend themselves to the inclusion of spare rows and/or columns that can be connected after fabrication to correct problems such as the gate to substrate shorts discussed above.
The gates in a CCD must be switched to both positive and negative potentials with respect to the substrate. Hence, a pad on the CCD used to drive the gates must be able to swing between −V1 and +V2 without a significant current flowing between the pad and substrate. However, if the voltage is significantly less than −V1 or greater than V2, the ESD protection circuit must be actuated to short the excess current to the substrate.
If a diode structure such as that described above is utilized to protect the circuit from voltage excursions above V2, the protection circuit will begin to conduct when the voltage on the pad goes above V2 or swings to a potential below 0. Hence, the protection circuit would short circuit the pad during the operation of the device when the pad is required to swing to −V1. In principle, this problem could be solved by utilizing a protection circuit consisting of two zener diodes of opposite polarity connected in series. However, construction of such pairs of diodes in the fabrication process used to construct CCD arrays is not practical.
It should also be noted that the CCD array can be damaged by charge buildup at a number of points in its fabrication or incorporation into a larger device in addition to the ESD events discussed above. Typically, the CCD chip is fabricated and then bonded to another substrate that includes the drive circuitry for the various electrodes. Damage from events that occur after the bonding to the drive substrate can be reduced by incorporating protection devices on the drive substrate. Such circuitry is not subject to the same fabrication limitations that limit the fabrication of the protection circuit on the CCD chip itself, and hence, conventional protection circuits can be utilized. However, protection circuitry on the drive substrate does not prevent damage that occurs prior to the bonding process. The CCD is subject to ESD during the handling of the wafers prior to bonding and during the bonding processes. In addition, some of the etching processes utilized after the electrodes have been fabricated over the oxide layer can lead to a charge buildup on the electrodes. This charge buildup can also damage the oxide layer.